Field of the Invention
The invention relates to a method for alignment and for exposure of a semiconductor wafer with a structural pattern in an exposure device.
On account of the constantly rising requirements in the fabrication of integrated circuits, the permissible tolerance deviations with regard to the structural widths of the structural elements formed and the relative positional accuracies of structural elements that are formed successively one above the other are becoming increasingly narrower. Therefore, during the lithographic projection of the structures for example from a mask onto semiconductor wafers or other plate-type objects such as, for example flat panels, etc., alignments marked in the x and y directions are patterned on the semiconductor wafers. With the aid of these alignment marks, the structural elements formed in a plane of the circuit can be brought to correspondence, with regard to the positioning, with those structural elements of a further plane which are currently to be formed in a lithographic projection. The substrate holder that receives the semiconductor wafer can generally be moved for this purpose. In this case, alignment marks formed will be compared in the exposure device with e.g. inserted reference marks which represent a positioning of the structural elements to be projected from the mask. The process of orienting the semiconductor wafer is also called alignment.
Before an exposure of a photosensitive resist that has already been applied usually occurs in a lithographic projection step, further physical or chemical processes take place on the semiconductor wafer and thus also on the alignment marks which represent the structures formed in the layer that was applied and patterned last with regard to their position. Said processes may lead to a leveling or deformation for the formation of asymmetries in the alignment marks or else a displacement of the original mark with regard to the newly applied layer. Particularly in the case where asymmetries occur, it is possible for a positional displacement of the center point of one or more alignment marks to be brought about unintentionally.
Examples of physical or chemical processes which may have a disadvantageous effect on the position or the form of an alignment mark are the deposition of layers such as, for instance aluminum or copper, chemical mechanical polishing steps such as, for instance, tungsten or oxide polishing or else resist spin effects during the application of photosensitive resists prior to the actual exposure. The result of the displacement of alignment marks is that the semiconductor wafer, in the exposure device, is oriented to a position which does not correspond to that position of the alignment mark actually concealed under an applied or modeled layer. Rather, the alignment position of the wafer is influenced by the processes affecting the signatures of the alignment marks in a superordinate or modeled layer. In the case of a metal deposition, by way of example, statistical distribution with regard to the positional accuracy with a magnitude of 80-100 nm (3-σ error) may occur if no corrections are applied during alignment.
The processes affecting the alignment marks often give rise to signatures which reflect a systematic effect in dependence on the position of the alignment marks on the semiconductor wafer. One example is radial effects which can occur e.g. during the deposition of a layer on the semiconductor wafer. A radial formation of displacement may also occur in polishing installations of specific construction. The further an alignment mark or a structural element is arranged toward the edge of the semiconductor wafer, the greater the extent to which the imaging of the alignment mark or of the element in the deposited layer is displaced towards the edge. A positional displacement in the form of a magnifying imaging of the underlying structures into the current layer takes place (magnification). The extent of these effects, i.e. the extent of the positional alteration of the alignment marks, generally has a linear relationship with the position on the wafer, for example the radius.
Exposure devices such as wafer scanners or wafer steppers are usually provided with the possibility of carrying out linear corrections during alignment for the purpose of exposing individual exposure fields. In this case, it is possible to correct the rotation, the translation, the aforementioned magnification and the wafer skew. On the basis of global alignment parameters, the corresponding corrections are performed in dependence on the position of the exposure field on the wafer.
These linear corrections have made it possible to considerably reduce the 3-σ errors in the x and y directions on the wafer. Using the aforementioned example of metal deposition, the corresponding error values for the positional accuracy have been able to be reduced to about 20 nm, for example. However, on account of the further increasing requirements with regard to the positional accuracy to be achieved, even these reduced values will be reached by prescribed tolerance limits in the near future.